Current Systems on a Chip (SOC) have grown more complicated than systems in the past. Systems in the future will have even more complexity than those of today. Complexity grows in many directions:                1) The system attempts to provide more features. In this situation, the number of blocks in the system increases to support the additional features.        2) The system attempts to do more on current metrics. For example, a camera may have more mega-pixels. Another example would be a turbo decoder that is upgraded to have a larger throughput. In this situation, each block either gets more complex or runs faster.        3) The system combines multiple legacy systems. For example, a simple phone has become a mobile phone, a camera, and a music player.        
As systems become complex, one notices several trends:                1) There are many blocks that are similar across the system (i.e. multiple Turbo decoders for the different modes). The resulting system has blocks that are similar and exist in several areas of the system. However, due to the architecture, the blocks cannot be reused in the different modes.        2) Processors run faster and get larger to provide the processing power required. The new processors take a larger gate count. Also, the power requirement for the processor increases. Furthermore, as the processor becomes more complicated, the interface requirements become more complicated. With this, the time/cycle required to communicate outside the processor increases as the interface grows more complex.        3) Systems become an amalgam of disparate systems. The interfaces between the disparate systems are ad hoc and inefficient.        4) The power required to run the system increases.        5) Interfaces between each block become more specialized and cannot be reused even though the functions may be similar.        
Referring to FIG. 1, there is illustrated in a block diagram a typical System on a Chip design (SOC) 10. SOC typically have:                1) Processor(s)        2) Memory        3) Blocks/Peripherals        4) Busses        
In the above, the blocks and processors are connected via the interconnect bus. Also, there are many disparate busses. As the number of blocks increase on a bus, the throughput decreases and/or the latency increases since the loading on the bus increases. Bridges are used to split the busses up so that the blocks that can take a larger latency of lower bandwidth can be “moved further away.”
In the example in FIG. 1, the processor, the DMA, the graphics accelerator, the on board memory, memory controller, and the 3 bridges are on the main bus. Typically, this is the fastest bus with the highest bandwidth. However, there are too many blocks in the system to put all on the main bus. Therefore, the three bridges provide the bridging services for the other blocks. There is a slow bus that has 3 blocks to support external interfaces. There is another bus to the communication system to talk to Blocks 1 to Block n. Also, there is a legacy system that is connected through the Legacy System Bridge.
There are many examples of busses. Some of the popular busses are APB, AHB, and OCP. One of the hallmarks of the busses is registers and memories are memory mapped.
Also, blocks/peripherals that need to communicate some information, status, or timing to another block uses an ad hoc scheme to communicate. This ad hoc scheme is typically customized for the specific interface and cannot be used for another interface. In FIG. 1, I/F #1 ad I/F #n are the ad hoc interface connecting the blocks so that the blocks can communicate. Also, the interrupts are not shown in FIG. 1.
Referring to FIGS. 2 and 3 there is illustrated an example of an ad hoc interface 20 and its timing diagram 30 of a block (for example. Block #n) in FIG. 1. The ad hoc interface for this example is for a viterbi decoder. The ad hoc interface is specialized for a viterbi decoder. This interface would not work for another block.
Blocks that need to communicate to the processor communicate in one of two ways:                1) The processor polls the blocks continuously.        2) The block interrupts the processor either directly or indirectly and the processor then goes gets the information.        
Furthermore, blocks can directly talk to other blocks. Typically, they share a tightly coupled interface (i.e. another specialized interface). Often, the interface has a tight handshake protocol.
Systems and methods disclosed herein provide a method and apparatus for data movement in a system on a chip to obviate or mitigate at least some of the aforementioned disadvantages.